The present invention relates generally to synchronous integrated circuits, and more specifically, to a control circuit for idling a synchronizing circuit during a refresh operation, such as in a synchronous dynamic random access memory device.
In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (SDRAMs), synchronous static random access memories (SSRAMs), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. In SDRAM devices, the memory core typically consists of an array of volatile dynamic random access memory (DRAM) cells. As well known in the art, DRAM cells are volatile because of the manner in which data is stored, namely, as the presence or absence of charge across a capacitor. Due to leakage currents inherent in the design of semiconductor DRAM cells, the capacitor can maintain its charge for only a finite time. As a result, the DRAM cells must be periodically “refreshed” in order to maintain the respective data states. The mechanism by which the memory cells of DRAM and SDRAM devices are refreshed is well known in the art.
With specific reference to SDRAM devices, the timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device typically must be synchronized to external operations. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device typically must be synchronized to external operations. For example, data are placed on a data bus by the memory device in synchronism with the external clock signal, and consequently, the memory device must provide the data to the bus at the proper times. To provide the data at the correct times, an internal clock signal is developed in response to the external clock signal, and is typically applied to latches contained in the memory device to thereby clock the data onto the data bus. The internal clock signal and external clock must be synchronized to ensure the internal clock signal clocks the latches at the proper times to successfully output the data at the proper times.
As used herein, the term synchronized includes signals that are coincident and signals that have a desired delay relative to one another. Additionally, in the present description, “external” is used to refer to signals and operations outside of the memory device, and “internal” to refer to signals and operations within the memory device. Moreover, although the present description is directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.
To synchronize external and internal clock signals in modern synchronous memory devices, a number of different approaches have been considered and utilized, including using clock synchronizing circuits that can generate an output clock signal synchronized with an input clock signal. Examples of conventional clock synchronizing circuits include delay-locked loops (DLLs), phased-locked loops (PLLs), and synchronous mirror delays (SMDs), as will be appreciated by those skilled in the art. As well known, conventional clock synchronizing circuits typically include a variable delay line that is used in generating a synchronized output clock signal. For example, in conventional DLLs, the variable delay line is part of a timing feedback loop. The phase difference between the input and output clock signals are compared, and a control signal indicative of the phase difference is generated. The control signal can then be used to incrementally adjust the variable delay line until the delay results in a synchronized output clock signal. When the appropriate delay time is achieved, the DLL is said to be “locked.” Even after the DLL is locked, the DLL constantly monitors for changes that affect the synchronization between the input and output clock signals, such as voltage variations, changes in operating temperature, and the like, and adjust the time delay accordingly in order to keep the synchronized output clock signal from excessively drifting out of synchronization.
The variable delay line is often formed from a number of serially-connected individual delay stages, with individual delay stages being added or removed to adjust the variable delay, as will be understood by those skilled in the art. For example, a plurality of serially-connected delay stages could be used to form the variable delay line, with one of the inputs of the different delay stages being selected as the entry point for the input clock signal in response to a control signal in order to control the length of the variable delay. A large number of stages in the variable delay line is desirable because each stage can have an incremental delay, which can provide better resolution in controlling the value of the variable delay. In addition, as well known, the lowest input clock frequency at which the DLL can operate is limited by the maximum variable delay that can be provided by the variable delay line.
The desired fine resolution and maximum variable delay that the variable delay line must provide can result in significant power consumption by the synchronizing clock circuit, which may be undesirable particularly where the memory device is used in a low-power application. For example, when the synchronous memory device is contained in a portable battery-powered device. One reason for greater power consumption when using more delay stages is the manner in which the input clock signal is applied to the delay stages of the variable delay line. As well known, each of the delay stages typically receives the input clock signal, and the delay time is adjusted by selecting the entry point of the input clock signal to the chain of delay stages. The input clock signal then propagates through the delay stages until being output by the last delay stage in the chain. It will be appreciated that the entry point may be in the “middle” of the chain of delay stages. Although the “upstream” delay stages are not used in synchronizing the output clock signal, they nevertheless are clocked by the input clock signal, causing the toggling of logic gates in each delay stage. The resulting switching current is wasted, since as previously discussed, the upstream delay stages are not utilized in generating the synchronized output clock signal. Additionally, the circuitry that is driven by the synchronized output clock signal, such as in the previously described case with synchronizing output data by clocking latches with the synchronized clock signal, will continue to consume power as the synchronized output clock signal transitions due to switching currents in the output circuitry.